Bài giảng Digital Systems - Chapter: Counters and Registerssc

Nội dung text: Bài giảng Digital Systems - Chapter: Counters and Registerssc

1. dce dce 2018 2018 Introduction • FFs and logic gates are combined to form various counters and registers. • Part 1 covers counter principles, various Digital Sytems counter circuits, and IC counters. • Part 2 covers several types of IC registers and Counters and Registers shift register counter troubleshooting. BK TP.HCM 2 dce dce 2018 Asynchronous (Ripple) Counters 2018 Four-bit asynchronous (ripple) counter • Review of four bit counter operation (refer to next slide) – Clock is applied only to FF A. J and K are high in all FFs to toggle on every clock pulse. – Output of FF A is CLK of FF B and so forth. – FF outputs D, C, B, and A are a 4 bit binary number with D as the MSB. – After the negative transistion of the 15th clock pulse the counter recycles to 0000. • This is an asynchronous counter because state is not changed in exact synchronism with the clock. MOD = the number of states 3 4 1
2. dce dce 2018 MOD-6 Counter 2018 Counters with MOD Number 000 – A BCD counter is a decade counter that counts from binary 0000 to 1001. • Decade counters are widely used for counting events and displaying results in decimal form. 11 12 3
3. dce dce 2018 Example 2018 Synchronous (Parallel) Counters • Show how to wire the 74LS293 as a MOD-14, MOD-60, • All FFs are triggered by CLK simultaneously counter with a 10-kHz clock input. • Mod-16 counter. – Each FF has J and K inputs connected so they are HIGH only when the outputs of all lower-order FFs are HIGH. – The total propagation delay will be the same for any number of FFs. • Synchronous counters can operate at much higher frequencies than asynchronous counters. 17 18 dce dce 2018 Synchronous (Parallel) Counters 2018 Synchronous (Parallel) Counters • Circuit Operation • Each FF should have its J&K inputs connected – On a given NGT of the clock, only those FFs that are such that they are HIGH only when the outputs of supposed to toggle on that NGT should have J=K=1 all lower-order FFs are in the HIGH state. when that NGT occurs. • Advantages over asynchronous: – FF A must change states at each NGT. Its J and K inputs 1. FFs will change states simultaneously; synchronized to arepermanently HIGH so that it will toggle on each NGT the NGTs of the input clock pulses. of the CLK input. 2. Propagation delays of the FFs do not add together to – FF B must change states on each NGT that occurs while produce the overall delay. A=1. 3. he total response time is the time it takes one FF to – FF C must change states on each NGT that occurs while toggle plus the time for the new logic levels to propagate A=B=1 through a single AND gate to reach the J, K inputs. – FF D must change states on each NGT that occurs while A=B=C=1 • total delay = FF tpd +AND gate tpd 19 20 5
4. dce dce 2018 MOD-8 synchronous up/down counter 2018 Presettable Counters • A presettable counter can be set to any desired starting point either asynchronously or synchronously. • The preset operation is also called parallel loading the counter. The counter counts up when the control input Up/Down = 1; A and B signals are passed it counts down when the control input Up/Down = 0; inverted A and B signals are passed 25 26 dce Synchronous counter with asynchronous dce 2018 2018 parallel load IC Synchronous Counters • 4 FFs, • PGT at the CLK input, • The counter can be preset to any value (applied to the A, B, C, and D inputs) by applying an active-low LOAD input. 27 28 7
5. dce dce 2018 2018 Extending Maximum Counting Range Using 74ALS163 (syn clear) and 74ALS191(async clear) MOD-16 counters for other MODs Synchronous load 0001-1100 mod-12 counter asynchronous load 0001-1011 mod-11 counter ( in 1100 state for a short period of time 33 34 dce dce 2018 Decoding a Counter 2018 Decoding a Counter • Decoding is the conversion of a binary output to a decimal value. Using AND • The active high decoder could be used to light an Gates to LED representing each decimal number 0 to 7. Decode a • Active low decoding is obtained by replacing the MOD-8 AND gates with NAND gates. Counter (produce pulse at specific count) 35 36 9
6. dce dce 2018 Choose a type of FF – JK in this example 2018 State table of counter example State transition diagram for the synchronous counter design Present State Next State J K JK Flip-Flop 0 0 0 x 0 1 1 x unused states excitation table Present State Next State J K 1 0 x 1 0 0 0 x 1 1 x 0 0 1 1 x 1 0 x 1 1 1 x 0 41 42 dce dce 2018 K maps for the J and K logic circuits 2018 K maps for the J and K logic circuits K map used to obtain the simplified expression for JA ; from the state table 43 44 11
7. dce dce 2018 State Table for Example: MOD-5 2018 K maps for Outputs - MOD-5 D-flip-flop counter Counter Using D-type Flip-Flops 49 50 dce dce 2018 Implementation of MOD-5, D flip-flop 2018 Integrated-Circuit Registers design • Registers can be classified by the way data is entered for storage, and by the way data is outputted from the register. – Parallel in/parallel out (PIPO) – Serial in/serial out (SISO) – Parallel in/serial out (PISO) – Serial in/parallel out (SIPO) 51 52 13
8. dce dce 2018 Shift Register Counters 2018 Four-bit Ring Counter • Ring Counter • Last FF shifts its value to first FF • Uses D-type FFs (JK FFs can also be used) – Must start with only one FF in the 1 state and all others in the 0 state. 57 58 dce dce 2018 MOD-6 Johnson counter 2018 HDL for Registers and Counters • Registers and counters can be described in HDL at Johnson counter either the behavioral or the structural level.  Also called a twisted ring • A structural level description shows the circuit in terms of counter a collection of components such as gates, flip-flops and  Same as ring multiplexers. counter but the inverted output of • In the behavioral, the register is specified by a the last FF is description of the various operations that it performs connected to input of the first similar to a function table. FF • The various components are instantiated to form a hierarchical description of the design similar to a representation of a logic diagram. 59 60 15
9. dce 2018 HDL for Registers and Counters (5) //Shift Registers module shift4 (D, LD, LI, Ck, Q); input [3:0] D; input LD, LI, Ck; output [3:0] Q; reg [3:0] Q; always @(posedge Ck) if (LD) Q <= D; else begin Q[0] <= Q[1]; Q[1] <= Q[2]; Q[2] <= Q[3]; Q[3] <= LI; end endmodule 65 17