The 8051 Microcontroller - Address Decoding - Lê Chí Thông

Nội dung text: The 8051 Microcontroller - Address Decoding - Lê Chí Thông

1. ĐH Bách Khoa TP.HCM Lê Chí Thông The 8051 Microcontroller Address Decoding Lê Chí Thông Ref. I. Scott Mackenzie, The 8051 Microcontroller Address Decoding • Address decoding is the process of generating chip select (CS) signals from the address bus for each device in the system. • The address bus lines are split into two sections: • The N most significant bits are used to generate the CS signals for different devices. • The M least significant bits are passed to the devices as addresses to the different memory cells . Ref. I. Scott Mackenzie Lê Chí Thông 2 sites.google.com/site/chithong 1
2. ĐH Bách Khoa TP.HCM Lê Chí Thông Full Address Decoding • Let’s assume the same microprocessor with 10 address lines ( 1 KB memory ). • Let’s assume we wish to implement 512 bytes memory using 128x8 memory chips. Ref. I. Scott Mackenzie Lê Chí Thông 5 Partial Address Decoding • Let’s assume the same microprocessor with 10 address lines ( 1 KB memory ). • Let’s assume we wish to implement 512 bytes memory using 128x8 memory chips. (Same requirements as the previous slide) Ref. I. Scott Mackenzie Lê Chí Thông 6 sites.google.com/site/chithong 3
3. ĐH Bách Khoa TP.HCM Lê Chí Thông Memory Organization Ref. I. Scott Mackenzie Lê Chí Thông 9 • Accessing External Code Memory o External code memory is ROM enabled by /PSEN signal. o Port 0 & Port 2 are unavailable as I/O ports. o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus. Ref. I. Scott Mackenzie Lê Chí Thông 10 sites.google.com/site/chithong 5
4. ĐH Bách Khoa TP.HCM Lê Chí Thông ADDRESS BUS [A0-A15] DATA BUS [D0-D7] U2 U1 A0 2 3 D0 D0 39 21 A8 A1 5 Q0 D0 4 D1 D1 38 P0.0/AD0 P2.0/A8 22 A9 A2 6 Q1 D1 7 D2 D2 37 P0.1/AD1 P2.1/A9 23 A10 A3 9 Q2 D2 8 D3 D3 36 P0.2/AD2 P2.2/A10 24 A11 A4 12 Q3 D3 13 D4 D4 35 P0.3/AD3 P2.3/A11 25 A12 A5 15 Q4 D4 14 D5 D5 34 P0.4/AD4 P2.4/A12 26 A13 A6 16 Q5 D5 17 D6 D6 33 P0.5/AD5 P2.5/A13 27 A14 A7 19 Q6 D6 18 D7 D7 32 P0.6/AD6 P2.6/A14 28 A15 Q7 D7 P0.7/AD7 P2.7/A15 11 ALE P1.0 1 10 RXD LE 1 P1.1 2 P1.0 P3.0/RXD 11 TXD OE P1.2 3 P1.1 P3.1/TXD 12 /INT0 74LS373 P1.3 4 P1.2 P3.2/INT0 13 /INT1 P1.4 5 P1.3 P3.3/INT1 14 T0 P1.5 6 P1.4 P3.4/T0 15 T1 P1.6 7 P1.5 P3.5/T1 16 /WR P1.7 8 P1.6 P3.6/WR 17 /RD C1 P1.7 P3.7/RD 19 30 ALE 18 X1 ALE 29 /PSEN X2 PSEN 30 pF Y1 31 9 EA C2 12 MHz +5 V RST 40 VCC +5 V +5 V 8951 30 pF C3 R1 10 uF 100 SW1 RESET R2 8.2 k Ref. I. Scott Mackenzie Lê Chí Thông 13 ROM U3 2764 U4 2764 A0 10 11 D0 A0 10 11 D0 A1 9 A0 O0 12 D1 A1 9 A0 O0 12 D1 A2 8 A1 O1 13 D2 A2 8 A1 O1 13 D2 A3 7 A2 O2 15 D3 A3 7 A2 O2 15 D3 A4 6 A3 O3 16 D4 A4 6 A3 O3 16 D4 A5 5 A4 O4 17 D5 A5 5 A4 O4 17 D5 A6 4 A5 O5 18 D6 A6 4 A5 O5 18 D6 A7 3 A6 O6 19 D7 A7 3 A6 O6 19 D7 A8 25 A7 O7 A8 25 A7 O7 A9 24 A8 A9 24 A8 A10 21 A9 A10 21 A9 A11 23 A10 A11 23 A10 A12 2 A11 A12 2 A11 A12 A12 +5 V /PSEN 22 +5 V /PSEN 22 27 OE 27 OE /CS0 20 PGM /CS1 20 PGM CE CE 1 1 VPP VPP 0000H-1FFFH 2000H-3FFFH Ref. I. Scott Mackenzie Lê Chí Thông 14 sites.google.com/site/chithong 7
5. ĐH Bách Khoa TP.HCM Lê Chí Thông EXTRA OUTPUT PORTS Eg. To output 0FH to this port MOV A,#0FH U8 D0 3 2 MOV DPTR,#4000H D1 4 D0 Q0 5 D1 Q1 MOVX @DPTR,A D2 7 6 D3 8 D2 Q2 9 D4 13 D3 Q3 12 ADDRESS: 4XXXH D5 14 D4 Q4 15 D6 17 D5 Q5 16 U9A 74LS02 D7 18 D6 Q6 19 /CS2 2 D7 Q7 1 11 /WR 3 1 LE OE 74LS373 Eg. To output F0H to this port MOV A,#0F0H U10 D1 3 2 MOV DPTR,#6000H D2 4 D0 Q0 5 D1 Q1 MOVX @DPTR,A D3 7 6 D4 8 D2 Q2 9 D5 13 D3 Q3 12 ADDRESS: 6XXXH D6 14 D4 Q4 15 D7 17 D5 Q5 16 U9B 74LS02 D8 18 D6 Q6 19 /CS3 5 D7 Q7 4 11 /WR 6 1 LE OE 74LS373 Ref. I. Scott Mackenzie Lê Chí Thông 17 +5 V EXTRA INPUT PORTS 10 K Eg. To input from this port MOV DPTR,#4000H U11 D0 2 18 MOVX A,@DPTR D1 3 A0 B0 17 D2 4 A1 B1 16 D3 5 A2 B2 15 D4 6 A3 B3 14 D5 7 A4 B4 13 ADDRESS: 4XXXH D6 8 A5 B5 12 D7 9 A6 B6 11 U12A 74LS32 A7 B7 /CS2 1 1 +5 V 3 19 DIR /RD 2 G 74LS245 10 K Eg. To input from this port MOV DPTR,#6000H U13 D1 2 18 MOVX A,@DPTR D2 3 A0 B0 17 D3 4 A1 B1 16 D4 5 A2 B2 15 D5 6 A3 B3 14 D6 7 A4 B4 13 ADDRESS: 6XXXH D7 8 A5 B5 12 D8 9 A6 B6 11 U12B 74LS32 A7 B7 /CS3 4 1 6 19 DIR /RD 5 G 74LS245 Ref. I. Scott Mackenzie Lê Chí Thông 18 sites.google.com/site/chithong 9