Bài giảng Digital Systems - Chapter 3: Objectives - Nguyễn Trần Hữu Nguyên

Nội dung text: Bài giảng Digital Systems - Chapter 3: Objectives - Nguyễn Trần Hữu Nguyên

1. dce dce 2017 2017 Chapter 3 Objectives • Selected areas covered in this chapter: – Operation of truth tables for AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit. – Boolean expression for logic gates. Digital Systems – DeMorgan’s theorems to simplify logic expressions. – Universal gates (NAND or NOR) to implement a circuit represented by a Boolean expression. – Concepts of active-LOW & active-HIGH logic signals. Nguyễn Trần Hữu Nguyên BK – Describing and measuring propagation delay time. TP.HCM D: Computer Engineering – Differences between an HDL and a computer E: nthnguyen@hcmut.edu.vn programming language. 2 1 2 dce dce 3-2 Truth Tables 2017 3-1 Boolean Constants and Variables 2017 • Boolean algebra allows only two values—0 and 1. • A truth table describes the relationship between – Logic 0 can be: false, off, low, no, open switch. the input and output of a logic circuit. – Logic 1 can be: true, on, high, yes, closed switch. • The number of entries corresponds to the number of inputs. – A 2-input table would have 22 = 4 entries. – A 3-input table would have 23 = 8 entries. • The three basic logic operations: – OR, AND, and NOT. 3 4 3 4 Digital Logic Design 1 1
2. dce dce 2017 3-3 OR Operation With OR Gates 2017 3-4 AND Operations with AND gates Example of the use of an OR • The AND operation is similar to multiplication: gate in an alarm system. X = A • B • C — Read as “X equals A AND B AND C” The + sign does not stand for ordinary multiplication—it stands for the AND operation. x is true (1) when A AND B AND C are true (1) Truth table — Gate symbol. 9 10 9 10 dce dce 2017 3-4 AND Operations with AND gates 2017 AND / OR Truth table/circuit symbol for a three input AND gate. The AND symbol on a logic- circuit diagram tells you output will go HIGH only when all inputs are HIGH. The OR symbol means the output will go HIGH when any input is HIGH. 11 12 11 12 Digital Logic Design 1 3
3. dce dce 2017 Boolean Operations 2017 3-6 Describing Logic Circuits Algebraically • If an expression contains both AND and OR Summarized rules for OR, AND and NOT gates, the AND operation will be performed first. • Unless there is a parenthesis in the expression. These three basic Boolean operations can describe any logic circuit. 17 18 17 18 dce dce 2017 3-6 Describing Logic Circuits Algebraically 2017 3-6 Describing Logic Circuits Algebraically • Whenever an INVERTER is present, output is • Further examples equivalent to input, with a bar over it. – Input A through an inverter equals A. 19 20 19 20 Digital Logic Design 1 5
4. dce dce 2017 3-7 Evaluating Logic Circuit Outputs 2017 3-7 Evaluating Logic Circuit Outputs • The next step is to fill in the values for column v. • The third step is to predict the values at node w which is the logical product of BC. v =AB — Node v should be HIGH when A (node u) is HIGH AND B is HIGH This column is HIGH whenever B is HIGH AND C is HIGH 25 26 25 26 dce dce 2017 3-7 Evaluating Logic Circuit Outputs 2017 3-7 Evaluating Logic Circuit Outputs • The final step is to logically combine columns v • Output logic levels can be determined directly and w to predict the output x. from a circuit diagram. – Output of each gate is noted until final output is found. • Technicians frequently use this method. Since x = v + w, the x output will be HIGH when v OR w is HIGH 27 28 27 28 Digital Logic Design 1 7
5. dce dce 2017 3-8 Implementing Circuits From Boolean Expressions 2017 3-9 NOR Gates and NAND Gates • Combine basic AND, OR, and NOT operations. – Simplifying the writing of Boolean expressions • Output of NAND and NOR gates may be found Circuit diagram to implement x = (A + B) (B + C) by determining the output of an AND or OR gate, and inverting it. – The truth tables for NOR and NAND gates show the complement of truth tables for OR and AND gates. 33 34 33 34 dce dce 2017 3-9 NOR Gates and NAND Gates 2017 3-9 NOR Gates and NAND Gates • The NOR gate is an inverted OR gate. Output waveform of a NOR gate for – An inversion “bubble” is placed at the output the input waveforms shown here. of the OR gate, making the Boolean output expression x = A + B 35 36 35 36 Digital Logic Design 1 9
6. dce dce 2017 3-10 Boolean Theorems 2017 3-10 Boolean Theorems Theorem (5) is straightforward, Theorem (1) states that if any variable as 0 added to anything does not is ANDed with 0, the result must be 0. affect value, either in regular addition or in OR addition. Theorem (2) is also obvious Theorem (6) states that if any variable by comparison with ordinary is ORed with 1, the is always 1. multiplication. Check values: 0 + 1 = 1 and 1 + 1 = 1. Prove Theorem (3) by trying each case. Theorem (7) can be proved by If x = 0, then 0 • 0 = 0 checking for both values of x: If x = 1, then 1 • 1 = 1 0 + 0 = 0 and 1 + 1 = 1. Thus, x • x = x Theorem (4) can be proved in the same manner. Theorem (8) can be proved similarly. 41 42 41 42 dce dce 2017 3-10 Boolean Theorems 2017 3-10 Boolean Theorems Multivariable Theorems Multivariable Theorems Commutative laws Theorems (14) and (15) do not have counterparts in ordinary algebra. Each can be proved by trying all possible cases for x and y. Analysis table & factoring Associative laws for Theorem (14) Distributive law 43 44 43 44 Digital Logic Design 1 11
7. dce dce 2017 3-12 Universality of NAND and NOR Gates 2017 3-12 Universality of NAND and NOR Gates How combinations of NANDs or NORs are How combinations of NANDs or NORs are used to create the three logic functions. used to create the three logic functions. It is possible, however, to implement any logic expression using NOR gates can be arranged to implement only NAND gates and no other type of gate, as shown. any of the Boolean operations, as shown. 49 50 49 50 dce dce 2017 3-12 Universality of NAND and NOR Gates 2017 3-12 Universality of NAND and NOR Gates A logic circuit to generate a signal x, that will go HIGH Possible Implementations # 1 whenever conditions A and B exist simultaneously, or whenever conditions C and D exist simultaneously. The logic expression will be x = AB + CD. Each of the TTL ICs shown here will fulfill the function. Each IC is a quad, with four identical gates on one chip 51 52 51 52 Digital Logic Design 1 13
8. dce dce 2017 3-13 Alternate Logic-Gate Representations 2017 3-13 Alternate Logic-Gate Representations Interpretation of the two NAND gate symbols. Interpretation of the two OR gate symbols. 57 58 57 58 dce dce 2017 3-14 Which Gate Representation to Use 2017 3-14 Which Gate Representation to Use Proper use of alternate gate symbols in the circuit diagram • When a logic signal is in the active state (HIGH or can make circuit operation much clearer. LOW) it is said to be asserted. • When a logic signal is in the inactive state (HIGH Original circuit using or LOW) it is said to be unasserted. standard NAND symbols. A bar over a signal Absence of a bar means asserted RD means asserted RD Equivalent representation (active) LOW. (active) HIGH where output Z is active-HIGH. Equivalent representation where output Z is active-LOW. 59 60 59 60 Digital Logic Design 1 15
9. dce dce 2017 2017 A typical CAD flow Summary so far for logic design • Boolean Algebra: a mathematical tool used in the analysis and design of digital circuits • OR, AND, NOT: basic Boolean operations • OR: HIGH output when any input is HIGH • AND: HIGH output only when all inputs are HIGH • NOT: output is the opposite logic level as the input • NOR: OR with its output connected to an INVERTER • NAND: AND with its output connected to an INVERTER • Boolean theorems and rules: to simplify the expression of a logic circuit and can lead to a simpler way of implementing the circuit • NAND, NOR: can be used to implement any of the basic Boolean operations 65 66 65 66 dce dce 2017 A simple logic fn and its Verilog module 2017 A simple logic fn and its Verilog module The module of a Verilog design unit describes what the design “looks like” on the inside i.e. what its behaviour and/or structure is Sensitivity list 67 68 67 68 Digital Logic Design 1 17
10. dce dce 2017 Hierarchical Verilog Code 2017 Hierarchical Verilog Code 73 74 73 74 dce 2017 Hierarchical Verilog Code 75 75 Digital Logic Design 1 19