Bài giảng Digital Logic Design 1 - Counters and Registers

Nội dung text: Bài giảng Digital Logic Design 1 - Counters and Registers

1. dce dce 2007 2009 Asynchronous (Ripple) Counters • Review of four bit counter operation (refer to next slide) – Clock is applied only to FF A. J and K are high in all Digital Logic Design 1 FFs to toggle on every clock pulse. – Output of FF A is CLK of FF B and so forth. – FF outputs D, C, B, and A are a 4 bit binary number Counters and Registers with D as the MSB. – After the negative transistion of the 15th clock pulse the counter recycles to 0000. BK TP.HCM • This is an asynchronous counter because state is not changed in exact synchronism with the clock. dce dce 2009 Four-bit asynchronous (ripple) counter 2009 Frequency division • The output frequency of each FF = the clock frequency of input / 2. • The output frequency of the last FF = the clock frequency / MOD. † MOD = the number of states dce dce 2009 Propagation Delay in Ripple Counters 2009 Ripple Counter Propagation Delay • Ripple counters are simple, but the cumulative 1MHz propagation delay can cause problems at high frequencies. • For proper operation the following apply: – Tclock ≥ N x tpd – Fmax = 1/(N x tpd) 10MHz Digital Logic Design 1
2. dce dce 2009 Asynchronous Down Counter 2009 IC Asynchronous counter dce dce 2009 Example 2009 Synchronous (Parallel) Counters • Show how to wire the 74LS293 as a MOD-16, MOD-10 • All FFs are triggered by CLK simultaneously counter with a 10-kHz clock input. Determine the frequency at Q3. • Mod-16 counter. –Each FF has J and K inputs connected so they are HIGH only when the outputs of all lower-order FFs are HIGH. –The total propagation delay will be the same for any number of FFs. • Synchronous counters can operate at much higher frequencies than asynchronous counters. dce dce 2009 Synchronous (Parallel) Counters 2009 Synchronous (Parallel) Counters • Circuit Operation • Each FF should have its J&K inputs connected – On a given NGT of the clock, only those FFs that are such that they are HIGH only when the outputs of supposed to toggle on that NGT should have J=K=1 all lower-order FFs are in the HIGH state. when that NGT occurs. • Advantages over asynchronous: – FF A must change states at each NGT. Its J and K inputs 1. FFs will change states simultaneously; synchronized to arepermanently HIGH so that it will toggle on each NGT the NGTs of the input clock pulses. of the CLK input. 2. Propagation delays of the FFs do not add together to – FF B must change states on each NGT that occurs while produce the overall delay. A=1. 3. he total response time is the time it takes one FF to – FF C must change states on each NGT that occurs while toggle plus the time for the new logic levels to propagate A=B=1 through a single AND gate to reach the J, K inputs. – FF D must change states on each NGT that occurs while A=B=C=1 • total delay = FF tpd +AND gate tpd Digital Logic Design 1
3. dce Synchronous counter with asynchronous dce 2009 2009 parallel load IC Synchronous Counters • 4 FFs, • PGT at the CLK input, • The counter can be preset to any value (applied to the A, B, C, and D inputs) by applying an active-low LOAD input. dce dce 2009 Synchronous Counter Example 2009 Synchronous Counter Example •start counting at t1 •synchronous clear at •start counting at t1 t2 •asynchronous clear at t2 •synchronous load at t3 •asynchronous clear at t3 •stop counting at t4 •stop counting at t4 (ENP (ENT low) low) •no counting at t5 •synchronous load at t5 (ENP low) •stop counting at t6 (ENT •resume counting at t6 low) •terminal state sets •continue counting at t7 RCO (ripple carry out) terminal state of 1001 sets high automatic reset at RCO t7 •stop counting at t8 (ENP) • RCO goes low at t9 due to low ENT (ENP does not affect RCO) dce dce 2009 74ALS190-75ALS191 series 2009 MOD-10 Counter synchronous counters (up/down) •Maximum state is 1001 •Max/min is high when state is 1001 and up-counting; or 0000 and down-counting •Max/min low at other times Figure 7-16 74ALS190-75ALS191 series synchronous counters: (a) logic symbol; (b) modules; (c) function table. Digital Logic Design 1
4. dce dce 2009 Analyzing Synchronous Counters 2009 Synchronous Counter Design • Determine desired number of bits and desired counting sequence • Draw the state transition diagram showing all possible states • Use the diagram to create a table listing all PRESENT states and their NEXT states •State transition • Add a column for each JK input (or other inputs). diagram and Indicate the level required at each J and K in order to timing diagram for produce transition to the NEXT state. synchronous • Design the logic circuits to generate levels required at counter each JK input. •unused states not • Implement the final expressions. in timing diagram dce dce 2009 Choose a type of FF – JK in this example 2009 State table of counter example State transition diagram for the synchronous counter design Present StateNext StateJ K JK Flip-Flop 000 x 011x unused states excitation table Present State Next State JK 10x1 000 x 11x0 011x 10x1 11x0 dce dce 2009 K maps for the J and K logic circuits 2009 K maps for the J and K logic circuits K map used to obtain the simplified expression for JA ; from the state table Digital Logic Design 1
5. dce dce 2009 74HC165 PISO Waveforms 2009 SIPO – The 74ALS164/74HC164 Ds = 0, CP INH = 0, Output values for given inputs (P0=P7) •8 bit shift register •Each FF output is externally accessible •A and B inputs are combined in an AND gate for serial input. •Shift occurs on NGT of the clock input. dce dce 2009 Other similar devices 2009 Shift Register Counters „ 74194/ASL194/HC194 • Ring Counter † 4 bit bi-directional universal shift register • Last FF shifts its value to first FF † Performs shift left, shift right, parallel in and parallel • Uses D-type FFs (JK FFs can also be used) out. „ 74373/ALS373/HC373/HCT373 – Must start with only one FF in the 1 state and † 8 bit PIPO with 8 D latches all others in the 0 state. † Tristate outputs „ 74374/ALS374/HC374 † 8 bit PIPO with 8 edge triggered D FFs, Tristate outputs dce dce 2009 Four-bit Ring Counter 2009 MOD-6 Johnson counter † Johnson counter „ Also called a twisted ring counter „ Same as ring counter but the inverted output of the last FF is connected to input of the first FF Digital Logic Design 1