Bài giảng Digital Systems - Chapter: FLIP-FLOPsc

Nội dung text: Bài giảng Digital Systems - Chapter: FLIP-FLOPsc

1. dce dce 2018 2018 Introduction • So far we have seen Combinational Logic – The output(s) depends only on the current values of the input variables Digital Systems • Here we will look at Sequential Logic circuits – The output(s) can depend on present and also past values of the input and the output variables FLIP-FLOPs • Sequential circuits exist in one of a defined number of states at any one time – They move "sequentially" through a defined sequence of BK transitions from one state to the next TP.HCM – The output variables are used to describe the state of a sequential circuit either directly or by deriving state variables from them 2 dce dce Synchronous and Asynchronous 2018 General Digital System 2018 Sequential Logic • Synchronous – The timing of all state transitions is controlled by a common clock – Changes in all variables occur simultaneously • Asynchronous – State transitions occur independently of any clock and normally dependent on the timing of transitions in the input variables – Changes in more than one output do not necessarily occur simultaneously • Clock – A clock signal is a square wave of fixed frequency – Often, transitions will occur on one of the edges of clock pulses • i.e. the rising edge or the falling edge 3 4 Digital Systems 1
2. dce dce 2018 Resetting the NAND Flip-Flop 2018 Function table of a NAND latch NAND 0 0 1 0 1 1 1 0 1 1 1 0 9 10 dce dce 2018 NAND Gate Latch 2018 Other Representations of a NAND latch • Summary of the NAND latch: – SET = RESET = 1. Normal resting state, outputs remain in state prior to input. – SET = 0, RESET = 1. Q will go high and remain high even if the SET input goes high. – SET = 1, RESET = 0. Q will go low and remain low even if the RESET input goes high. – SET = RESET = 0. Output is unpredictable because the latch is being set and reset at the same time. • Symbols indicate Q is set (high) when S is low. 11 12 Digital Systems 3
3. dce dce 2018 SR latch useful when temporary setting is used to 2018 activate switch Digital Pulses The NAND FF is used to • The transition from low to high on a positive provide a bounce free switch pulse is called rise time (t ). so that the 1 KHz pulse can r propagate to the output – Rise time is measured between the 10% and 90% without distortion. points on the leading edge of the voltage waveform. • The transition from high to low on a positive pulse is called fall time (tf). – Fall time is measured between the 90% and 10% points on the trailing edge of the voltage waveform. 17 18 dce dce 2018 Rise and Fall times 2018 Rise and Fall times Signal that activates an active-low output with: tw = 50ns, tr =15ns, and tf = 10 ns. 19 20 Digital Systems 5
4. dce dce 2018 Clock Signals and Clocked Flip-Flops 2018 Clocked S-R Flip-Flop • The SET-RESET (or SET-CLEAR) FF will change states • Setup time (tS) is the minimum time interval before the active CLK transition that the control input must be at the positive going or negative going clock edge. kept at the proper level. • Hold time (tH) is the time after the active CLK transition during which the control input must kept at the proper level. 25 26 dce dce 2018 Clocked SR Flip-Flop 2018 Clocked SR Flip-Flop • Clocked S-R flip-flop that triggers only on negative-going • Implementation of edge-detector circuits used in edge- transitions. triggered flip-flops: (a) PGT; (b) NGT. The duration of the CLK* pulses is typically 2–5 ns. • Simplified version of the internal circuitry for an edge- triggered S-R flip- flop. 27 28 Digital Systems 7
5. dce dce 2018 2018 Clocked D Flip-Flop Problem 5-13 The waveforms below are to be applied to two different FF’s. • One data input. Draw Q for (a) positive edge-triggered (b) negative edge-triggered. • The output changes to the value of the input at either the positive going or negative going clock trigger. 33 34 dce dce 2018 Edge-triggered D flip-flop 2018 Parallel transfer of binary data using D flip-flops implementation from a J-K flip-flop 35 36 Digital Systems 9
6. dce dce 2018 2018 Asynchronous Inputs Problem: Compare the operation of the D latch with the negative edge-triggered D FF using the following • Inputs that depend on the clock are synchronous. waveforms. • Most clocked FFs have asynchronous inputs that do not depend on the clock. • The labels PRE and CLR are used for asynchronous inputs. • Active low asynchronous inputs will have a bar over the labels and inversion bubbles. • If the asynchronous inputs are not used they will be tied to their inactive state. 41 42 dce dce 2018 Clocked J-K flip-flop with asynchronous inputs 2018 Clocked J-K flip-flop with asynchronous inputs 43 44 Digital Systems 11
7. dce dce 2018 Clock LOW and HIGH time 2018 Potential Timing Problems in FF Circuits • When the output of one FF is connected to the input of another FF and both devices are triggered by the same clock, there is a potential timing problem. synchronous asynchronous • Propagation delay may cause unpredictable outputs. t is the minimum time that the CLK must remain low before it w(L) • The low hold time parameter of most FFs mean goes high. this won’t normally be a problem. tw(H) is the minimum time that the CLK must remain high before it goes low. Similarly for asynchronous signals - but may have a different value than the CLK signal. 49 50 dce dce 2018 Propagation Delay in Synchronous Circuits 2018 Flip-Flop Synchronization • Most systems are primarily synchronous in operation, in that changes depend on the clock. •The input (J2) to Q2 must • Asynchronous and synchronous be held for t after the H operations are often combined. clock edge. • The random nature of asynchronous •This will occur only if tPHL inputs can result in unpredictable results. > tH. •Usually, this is the case. 51 52 Digital Systems 13
8. dce dce 2018 Synchronous transfer of contents of register X into 2018 register Y Serial Data Transfer: Shift Registers • When FFs are arranged as a shift register, bits will shift with each clock pulse. • FFs used as shift registers must have very low hold time parameters to perform predictably. Modern FFs have tH values well within what is required. • The direction of data shifts will depend on the circuit requirements and the design. 57 58 dce dce 2018 Serial Data Transfer: Shift Registers 2018 Four-bit Shift Register • Parallel transfers – register contents are transferred simultaneously with a single clock cycle. • Serial transfers – register contents are transferred one bit at a time, with a clock pulse for each bit. • Serial transfers are slower, but the circuitry is simpler. Parallel transfers are faster, but circuitry is more complex. • Serial and parallel are often combined to exploit the benefits of each. 59 60 Digital Systems 15
9. dce dce 2018 Microcomputer Application 2018 Example of Microprocessor Interfacing • Microprocessor units (MPUs) which will be studied later, perform many functions that involve the use of registers for data transfer and storage. • MPUs may send data to external registers for many purposes, including: – Solenoid or relay control – Motor starting – Device positioning – Motor speed controls 65 66 dce dce 2018 Schmitt-Trigger Devices 2018 Schmitt-Trigger Response (two thresholds) • Not a FF but shows a memory characteristic • Accepts slow changing signals and produces a signal that transitions quickly. • A Schmitt trigger device will not respond to an input until it exceeds the positive or negative going threshold. • There is a separation between the two threshold levels. This means that the device will “remember” the last threshold exceeded until the input goes to the opposite threshold. Standard inverter response to slow noisy input, and (b) Schmitt-trigger response to slow noisy input. Often used with noisy signals 67 68 Digital Systems 17
10. dce dce 2018 Logic symbols for the 74121 nonretriggerable 2018 one-shot Clock Generator Circuits • FFs have two stable states, so are considered bistable multivibrators. • One shots have one stable state and are considered monostable multivibrators. • Astable or free-running multivibrators switch back and forth between two unstable states. This makes it useful for generating clock signals for synchronous circuits. • Crystal control may be used if a very stable clock is needed. Crystal control is used in microprocessor based systems and microcomputers where accurate timing intervals are essential. 73 74 dce dce 2018 Clock Generator Circuit: Schmitt-trigger Oscillator 2018 Clock Generator Circuit: 555 Timer 555 timer IC used astable multivibrator. Schmitt-trigger oscillator using a 7414 INVERTER. A 7413 Schmitt-trigger NAND may also be used. Circuit will not oscillate if R is not kept within these limits. 75 76 Digital Systems 19
11. dce dce 2018 2018 Verilog codes for T & J-K Flip-Flops J-K Flip-Flop //T flip-flop from D flip-flop and //JK flip-flop from D flip-flop and gates gates // Functional description of JK // flip-flop module TFF (Q,T,CLK,RST); module JKFF (Q,J,K,CLK,RST); module JK_FF (J,K,CLK,Q,Qnot); output Q; output Q; output Q,Qnot; input J,K,CLK; • Here the flip-flop is described input T,CLK,RST; input J,K,CLK,RST; using the characteristic table reg Q; wire DT; wire JK; rather than the characteristic assign Qnot = ~ Q ; equation. assign DT = Q ^ T ; assign JK = (J & ~Q) | (~K & Q); always @(posedge CLK) • The case multiway branch //Instantiate the D flip-flop //Instantiate D flipflop case({J,K}) condition checks the 2-bit DFF TF1 (Q,DT,CLK,RST); DFF JK1 (Q,JK,CLK,RST); number obtained by 2'b00: Q = Q; concatenating the bits of J and endmodule endmodule 2'b01: Q = 1'b0; K. 2'b10: Q = 1'b1; Characteristic equations of the flip-flops: • The case value ({J,K}) is 2'b11: Q = ~ Q; evaluated and compared with the values in the list of Q(t 1) Q T for a T flip - flop endcase statements that follow. endmodule Q(t 1) JQ' K'Q for a JK flip - flop 81 82 dce dce 2018 D-Flip-Flop 2018 The signals A and B are applied to the inputs of an SR flip- //Positive Edge triggered DFF with Reset flop (or Set-Clear FF), a transparent latch and a D-type flip- module DFF(CLK,RST,D,Q); flop. Sketch the waveforms at W, X, Y and Z. input CLK,RST,D; output Q; reg Q; always@(posedge CLK or posedge RST) if (RST) Q<=0; else Q<=D; endmodule 83 84 Digital Systems 21