Bài giảng Logic Synthesis Technology Mapping - Biện Quang Hoàng

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1. Contents Logic Synthesis • 1. Technology Libraries • 2. What is Technology Mapping (TM)? Technology Mapping • 3. Graph Covering • 4. TM by Tree Covering • 5. Optimal Tree Covering Presenter: • 6. Q&A Biện Quang Hoàng • 7. Reference Lương NgọcNhơn 1. Technology Libraries Gate library example • Gate is primitive element • Gates are inverter, NAND , NOR gate and complex gates: NOR, XOR gates • Technology library consists of a finite collection of gates
2. 3. Graph Covering Subject DAG • TM is based on graph covering • Realization Or Pattern for each library gate in terms of 2‐input NAND and inverter • Cover is a collection of a pattern graphs • Realization or Pattern is a primitive DAG • Each node in Boolean network can be replaced by NAND gate • Form of Boolean network is a subject DAG • Each gate is a form in Figure7.6 Boolean network to NAND Primitive DAG network
3. Single‐cone partition 3‐input NAND is Step 2: Decomposition decomposed into • Each node in Boolean network can be NAND2 replaced by NAND gate • Each node in a NAND tree is replaced by n‐ input NAND tree is decomposed into a NAND2‐tree •
4. 6. Q&A • Cmap(10, NAND2) min Æ choose this cover 7. Reference • Chapter 7.7 and 7.8 of Logic Senthesis– SrinivasDevadas, AbhijitGhosh, Kurt Keutzer • VLSI System Design Course • Tsuyoshi Isshiki Dept. Communications and Integrated Systems , Tokyo Institute of Technology •