The 8051 Microcontroller - Chapter 2: Hardware Summary - Lê Chí Thông

Nội dung text: The 8051 Microcontroller - Chapter 2: Hardware Summary - Lê Chí Thông

1. ĐH Bách Khoa Tp.HCM Lê Chí Thông The 8051 Microcontroller Chapter 2 Hardware Summary Lê Chí Thông Ref. I. Scott Mackenzie, The 8051 Microcontroller Features of 8051 • 4KB ROM • 128 bytes RAM • Four 8-bit I/O ports • Two 16-bit timers • Serial interface • 64KB external code memory space Ref. I. Scott Mackenzie• 64KB external Lêdata Chí Thông memory space 2 sites.google.com/site/chithong 1
2. ĐH Bách Khoa Tp.HCM Lê Chí Thông Address/Data Buses Multiplexing Parallel I/O Serial I/O FIGURE 2–2 8051 pinouts Ref. I. Scott Mackenzie Lê Chí Thông 5 Around The Pins • Port 0 : dual purpose o I/O port o Multiplexed address and data bus (AD0-AD7) • Port 1 : I/O port • Port 2 : dual purpose o I/O port o High-byte address bus (A8-A15) Ref. I. Scott Mackenzie Lê Chí Thông 6 sites.google.com/site/chithong 3
3. ĐH Bách Khoa Tp.HCM Lê Chí Thông • ALE (Address Latch Enable) o Use to demultiplex the address and data bus Ref. I. Scott Mackenzie Lê Chí Thông 9 • /EA (External Access) It is tied to +5V or ground. o /EA = +5V: executes programs from internal ROM o /EA = 0V: executes programs from external ROM Ref. I. Scott Mackenzie Lê Chí Thông 10 sites.google.com/site/chithong 5
4. ĐH Bách Khoa Tp.HCM Lê Chí Thông FIGURE 2–5 Relationship between oscillator clock cycles, states, and the machine cycle A machine cycle is 12 oscillator periods. Use 12 MHz crystal: a machine cycle is 1 µs Ref. I. Scott Mackenzie Lê Chí Thông 13 • Vdd , Vss : Power connections o Vdd is connected to +5V o Vss is connected to ground (0V) Ref. I. Scott Mackenzie Lê Chí Thông 14 sites.google.com/site/chithong 7
5. ĐH Bách Khoa Tp.HCM Lê Chí Thông FIGURE 2–6 Summary of the 8031 memory spaces Memory Map 256-byte 64-Kbyte Ref. I. Scott Mackenzie Lê Chí Thông 17 • Internal (on-chip) data memory o Register banks (00H-1FH) o Bit-addressable RAM (20H-2FH) o General-purpose RAM (30H-7FH) o Special function registers (80H-FFH) Ref. I. Scott Mackenzie Lê Chí Thông 18 sites.google.com/site/chithong 9
6. ĐH Bách Khoa Tp.HCM Lê Chí Thông • Bit-addressable RAM o 16 bytes from (byte) addresses 20H to 2FH o 128 bits from bit addresses 00H to 7FH o Bit can be set, cleared, ANDed, ORed, Ex: To set bit 67H SETB 67H or MOV A, 2CH ORL A, #10000000B MOV 2CH, A Ref. I. Scott Mackenzie Lê Chí Thông 21 • Register banks o Bank 0 (default), Bank 1, Bank 2, and Bank 3 o Change register bank by selecting bits RS1 and RS0 the program status word o One bank includes 8 registers: R0 through R7 Ex: Read the contents of location 05H into the accumulator MOV A, R5 or MOV A, 05H Write the contents of the accumulator into location 00H MOV R0, A Ref. I. Scott Mackenzie Lê Chí Thông 22 sites.google.com/site/chithong 11
7. ĐH Bách Khoa Tp.HCM Lê Chí Thông • A and B Register o A (accumulator) register (Address E0H)  The most versatile register  Used for many operations (addition, subtraction, multiplication, division, Boolean bit manipulations, ) o B register (Address F0H)  Used with the A register for multiplication and division Ex: To multiply the 8-bit unsigned values in A and B and leaves the 16-bit result in A (low-byte) and B (high-byte) MUL AB To divide A by B and leaves the integer result in A and the remainder in B DIV AB Ref. I. Scott Mackenzie Lê Chí Thông 25 • Stack Pointer (SP) (Address 81H) o Used to access the stack o PUSH : SP increases before storing data on the stack o POP : data is read from the stack and then SP decreases o The reset value of SP is 07H
   Stack is from 08H o LIFO : Last In First Out Ex: To set the stack beginning at 60H MOV SP,#5FH To store data from R1 register into stack PUSH 01H To retrieve data from stack to register R2 POP 02H Ref. I. Scott Mackenzie Lê Chí Thông 26 sites.google.com/site/chithong 13
8. ĐH Bách Khoa Tp.HCM Lê Chí Thông • Data Pointer (DPTR) (Addresses 82H & 83H) o Used to access external code or data memory o DPTR is 16-bit register, including DPH (high-byte) and DPL (low-byte) Ex: To write 55H into external RAM location 1000H MOV A,#55H MOV DPTR,#1000H MOVX @DPTR,A Ref. I. Scott Mackenzie Lê Chí Thông 29 • Port Register o P0 , P1 , P2 , and P3 registers o Used to access I/O ports o Ports 0, 2, and 3 may not available for I/O if external memory is used or if some of special features are used (interrupt, ) o All ports are bit-addressable Ex: To read data from Port 1 into A register MOV A,P1 To write data from R7 register to Port 2 MOV P2,R7 To set bit 7 of Port 3 SETB P3.7 To clear bit 7 of Port 1 CLR P1.7 or CLR 97H Ref. I. Scott Mackenzie Lê Chí Thông 30 sites.google.com/site/chithong 15
9. ĐH Bách Khoa Tp.HCM Lê Chí Thông • Interrupt Registers o 8051 has a 5-source, 2-priority level interrupt structure . o The Interrupt Register ( IE ) is used to enable interrupts. o The Interrupt Priority Register ( IP ) is used to set the priority level. (discussed in details in Chapter 6) Ref. I. Scott Mackenzie Lê Chí Thông 33 • Power Control Register (PCON) Ref. I. Scott Mackenzie Lê Chí Thông 34 sites.google.com/site/chithong 17
10. ĐH Bách Khoa Tp.HCM Lê Chí Thông FIGURE 2–10 Read timing for external code memory Timing diagram for external CODE memory access Ref. I. Scott Mackenzie Lê Chí Thông 37 • Accessing External Data Memory o External code memory is RAM enabled by /RD & /WR signals using MOVX instruction. o Port 0 & Port 2 are unavailable as I/O ports. o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus. Ref. I. Scott Mackenzie Lê Chí Thông 38 sites.google.com/site/chithong 19
11. ĐH Bách Khoa Tp.HCM Lê Chí Thông FIGURE 2–13 Address decoding ROM RAM Ref. I. Scott Mackenzie Lê Chí Thông 41 • Overlapping the External Code and Data Spaces o A RAM can occupy code and data memory space by using the following circuit. For external CODE and DATA memory Ref. I. Scott Mackenzie Lê Chí Thông 42 sites.google.com/site/chithong 21