Bài giảng Digital Logic Design 1 - Arithmetic

Nội dung text: Bài giảng Digital Logic Design 1 - Arithmetic

1. dce dce 2007 2009 Introduction • Digital circuits are frequently used for arithmetic operations • Fundamental arithmetic operations on binary Digital Logic Design 1 numbers and digital circuits which perform arithmetic operations will be examined. Arithmetic BK TP.HCM dce dce 2009 Binary Addition 2009 Binary Addition • Binary numbers are added like decimal • 0 + 0 = 0 numbers. • 1 + 0 = 1 • In decimal, when numbers sum more than 9 a • 1 + 1 = 0 + carry 1 carry results. • 1 + 1 + 1 = 1 + carry 1 • In binary when numbers sum more than 1 a • E.g.: carry takes place. 1010 (10)001 (1) • Addition is the basic arithmetic operation used by digital devices to perform subtraction, +1100 (12) +101 (5) multiplication, and division. 10110 (22) +111 (7) 1101 (13) dce dce 2009 Representing Signed Numbers 2009 Representing Signed Numbers • Since it is only possible to show • So far, numbers are assumed to be unsigned (i.e. positive) magnitude with a binary number, the sign • How to represent signed numbers? • Solution 1: Sign-magnitude - Use one bit to represent the (+ or −) is shown by adding an extra sign, the remain bits to represent magnitude “sign” bit. +27 = 0001 1011 b • A sign bit of 0 indicates a positive number. -27 = 1001 1011 b • A sign bit of 1 indicates a negative – Problem: need to handle sign and magnitude separately. number. • Solution 2: One’s complement - If the number is •The 2’s complement system is the most negative, invert each bits in the magnitude commonly used way to represent signed +27 = 0001 1011 b numbers. -27 = 1110 0100 b • Not convenient for arithmetic - add 27 to -27 results in 1111 1111b – Two zero values Digital Logic Design 1
2. dce dce 2009 2009 Addition in the 2’s Complement System Subtraction in the 2’s Complement System • Perform normal binary addition of magnitudes. • The number subtracted (subtrahend) is negated. • The result is added to the minuend. • The answer represents the difference. • If the answer exceeds the number of magnitude bits an overflow results. dce dce 2009 Multiplication 2009 Binary Division • In decimal, multiplying by 10 can be achieved • This is similar to decimal long division. by • It is simpler because only 1 or 0 are possible. – shifting the number left by one digit adding a zero at • The subtraction part of the operation is done the LS digit using 2’s complement subtraction. • In binary, this operation multiplies by 2 • If the signs of the dividend and divisor are the N • In general, left shifting by N bits multiplies by 2 same the answer will be positive. – zeros are always brought in from the right-hand end • If the signs of the dividend and divisor are –E.g. different the answer will be negative. dce dce 2009 Summary of Signed and Unsigned Numbers 2009 BCD Addition Unsigned Signed • When the sum of each decimal digit is less than MSB has a positive value (e.g. +8 MSB has a negative value (e.g. -8 9, the operation is the same as normal binary for for addition. a 4-bit system) a 4-bit system) The carry-out from the MSB of an To avoid overflow in an adder, • When the sum of each decimal digit is greater adder can be used as an extra bit need to sign extend and use an than 9, a binary 6 is added. This will always of the answer to avoid overflow adder with one more bit than the numbers to be added cause a carry. To increase the number of bits, To increase the number of bits, add zeros to the left-hand side sign extend by duplicating the MSB Complementing and adding 1 Complementing and adding 1 converts X to (2N - X) converts X to -X Digital Logic Design 1
3. dce dce 2009 Full Adder 2009 Circuitry for a full adder •Truth Table • Boolean Equations dce dce 2009 Full Adder from Half Adders 2009 Parallel Adder •Truth Table • Uses 1 full adder per bit of the numbers • The carry is propagated from one stage to the next most significant stage – takes some time to work because of the carry propagation delay which is n times the propagation delay of one stage. • Boolean Equations dce dce 2009 2009 Complete Parallel Adder With Registers Complete Parallel Adder With Registers • Register notation – to indicate the contents of a register we use brackets: [A]=1011 is the same as A3=1, A2=0, A1=1, A0=1 • A transfer of data to or from a register is indicated with an arrow –[B]→[A] means the contents of register B have been transferred to register A. • Eg.: 1001 + 0101 using the parallel adder: –t1 : A CLR pulse is applied –t2 : 1001 from mem-> B –t3 : 1001 + 0000 -> A –t4 : 0101 from mem-> B –t5 : The sum outputs -> A –The sum of the two numbers is now present in the accumulator. Digital Logic Design 1
4. dce dce 2009 Two 74HC382 ALU chips connected as an 2009 Troubleshooting Case Study eight-bit adder • Read the case study in the text and determine the most likely fault in the circuit shown, given the test results described. Digital Logic Design 1