Bài giảng Digital Logic Design 1 - FLIP-FLOP

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1. dce dce 2007 2009 Introduction • So far we have seen Combinational Logic – The output(s) depends only on the current values of the input variables Digital Logic Design 1 • Here we will look at Sequential Logic circuits – The output(s) can depend on present and also past values of the input and the output variables FLIP-FLOP • Sequential circuits exist in one of a defined number of states at any one time – They move "sequentially" through a defined sequence of BK transitions from one state to the next TP.HCM – The output variables are used to describe the state of a sequential circuit either directly or by deriving state variables from them dce dce Synchronous and Asynchronous 2009 General Digital System 2009 Sequential Logic • Synchronous – The timing of all state transitions is controlled by a common clock – Changes in all variables occur simultaneously • Asynchronous – State transitions occur independently of any clock and normally dependent on the timing of transitions in the input variables – Changes in more than one output do not necessarily occur simultaneously •Clock – A clock signal is a square wave of fixed frequency – Often, transitions will occur on one of the edges of clock pulses • i.e. the rising edge or the falling edge dce General flip-flop symbol and definition of its two dce 2009 2009 possible output states NAND Gate Latch • The NAND gate latch or simply latch is a basic FF. • The inputs are set and clear (reset) • The inputs are active low, that is, the output will change when the input is pulsed low. • When the latch is set • We now introduce the concept of memory. The flip- Q =1 and Q = 0 flop, abbreviated FF, is a key memory element. • When the latch is clear or reset • The outputs of a flip flop are Q and Q’ • Q is understood to be the normal output, Q’ is always Q = 0 and Q = 1 the opposite. Digital Logic Design 1
2. dce dce 2009 Determine Q 2009 NOR Gate Latch • The NOR latch is similar to the NAND latch except that the Q and Q’ outputs are reversed. • The SET and RESET inputs are active high, that is, the output will change when the input is pulsed high. • In order to ensure that a FF begins operation at a known level, a pulse may be applied to the SET or RESET inputs when a device is powered up. dce dce 2009 NOR gate latch 2009 Digital Pulses • (a) NOR gate latch; (b) function table; (c) simplified block symbol. • The transition from low to high on a positive pulse is called rise time (tr). – Rise time is measured between the 10% and 90% points on the leading edge of the voltage waveform. • The transition from high to low on a positive pulse is called fall time (tf). • Determine Q for a NOR latch given the inputs below – Fall time is measured between the 90% and 10% points on the trailing edge of the voltage waveform. dce dce 2009 Rise and Fall times 2009 Clock Signals and Clocked Flip-Flops • Asynchronous system – outputs can change state at any time the input(s) change. • Synchronous system – output can change state only at a specific time in the clock cycle. – The clock signal is a rectangular pulse train or square wave. – Positive going transition (PGT) – when clock pulse goes from 0 to 1. – Negative going transition (NGT) – when clock pulse goes from 1 to 0. – Transitions are also called edges. Digital Logic Design 1
3. dce dce 2009 Clocked SR Flip-Flop 2009 Clocked J-K Flip-Flop • Implementation of edge-detector circuits used in edge- triggered flip-flops: (a) PGT; (b) NGT. The duration of the • Operates like the S-R FF. J is set, K is clear. CLK* pulses is typically 2–5 ns. • When J and K are both high the output is toggled from whatever state it is in to the opposite state. • May be positive going or negative going clock trigger. • Has the ability to do everything the S-C FF does, plus operate in toggle mode. dce dce 2009 Clocked JK Flip-Flop 2009 Edge-triggered J-K flip-flop CLK* must be high for FF to change states. This condition only occurs at the edge of a CLK transition. dce dce 2009 2009 Edge-triggered D flip-flop Clocked D Flip-Flop implementation from a J-K flip-flop • One data input. • The output changes to the value of the input at either the positive going or negative going clock trigger. Digital Logic Design 1
4. dce dce 2009 Flip-Flop Timing Considerations 2009 Flip–Flop Propagation Delays • Important timing parameters: – Setup and hold times – Propagation delay: the time for a signal at the input to be shown at the output. – Maximum clocking frequency: highest clock frequency that will give a reliable output. – Clock pulse high and low times: minimum time that the clock must be high before going low, and low before going high. – Asynchronous active pulse width: the minimum time PRESET or CLEAR must be held for the FF to set or clear reliably. – Clock transition times: maximum time for the clock transitions, generally less than 50 ns for TTL, or 200 ns for CMOS devices. dce dce 2009 Clock LOW and HIGH time 2009 Potential Timing Problems in FF Circuits • When the output of one FF is connected to the input of another FF and both devices are triggered by the same clock, there is a potential timing problem. synchronousasynchronous • Propagation delay may cause unpredictable outputs. t is the minimum time that the CLK must remain low before it w(L) • The low hold time parameter of most FFs mean goes high. this won’t normally be a problem. tw(H) is the minimum time that the CLK must remain high before it goes low. Similarly for asynchronous signals - but may have a different value than the CLK signal. dce dce 2009 Propagation Delay in Synchronous Circuits 2009 Flip-Flop Synchronization • Most systems are primarily synchronous in operation, in that changes depend on the clock. •The input (J2) to Q2 must • Asynchronous and synchronous be held for t after the H operations are often combined. clock edge. • The random nature of asynchronous •This will occur only if tPLH inputs can result in unpredictable results. > tH. •Usually, this is the case. Digital Logic Design 1
5. dce dce 2009 Serial Data Transfer: Shift Registers 2009 Four-bit Shift Register • Parallel transfers – register contents are transferred simultaneously with a single clock cycle. • Serial transfers – register contents are transferred one bit at a time, with a clock pulse for each bit. • Serial transfers are slower, but the circuitry is simpler. Parallel transfers are faster, but circuitry is more complex. • Serial and parallel are often combined to exploit the benefits of each. dce dce 2009 Serial transfer from X register into Y register 2009 Frequency Division and Counting • FFs are often used to divide a frequency as illustrated in next slide. Here the output frequency is 1/8th the input (clock) frequency. • The same circuit is also acting as a binary counter. The outputs will count from 0002 to 1112 • The number of states possible in a counter is the modulus or MOD number. Next slide is a MOD-8 (23) counter. If another FF is added it would become a MOD-16 (24) counter. dce dce 2009 MOD-8 Asynchronous Counter 2009 State Table & Diagram of MOD-8 Asynchronous Counter Digital Logic Design 1
6. dce dce 2009 Logic symbols for the 74121 nonretriggerable 2009 one-shot Clock Generator Circuits • FFs have two stable states, so are considered bistable multivibrators. • One shots have one stable state and are considered monostable multivibrators. • Astable or free-running multivibrators switch back and forth between two unstable states. This makes it useful for generating clock signals for synchronous circuits. • Crystal control may be used if a very stable clock is needed. Crystal control is used in microprocessor based systems and microcomputers where accurate timing intervals are essential. dce dce 2009 Clock Generator Circuit: Schmitt-trigger Oscillator 2009 Clock Generator Circuit: 555 Timer 555 timer IC used astable multivibrator. Schmitt-trigger oscillator using a 7414 INVERTER. A 7413 Schmitt-trigger NAND may also be used. Circuit will not oscillate if R is not kept within these limits. Digital Logic Design 1