Bài giảng Digital System - Chapter 3: Combinational Circuits -Tran Ngoc Thinh

Nội dung text: Bài giảng Digital System - Chapter 3: Combinational Circuits -Tran Ngoc Thinh

1. dce dce 2016 2016 Introduction • Basic logic gate functions will be combined in combinational logic circuits. • Simplification of logic circuits will be done using Chapter 3: Combinational Circuits Boolean algebra and a mapping technique. • Troubleshooting of combinational circuits will be introduced. Tran Ngoc Thinh BK TP.HCM HCMC University of Technology 2 dce dce 2016 Sum-of-Products & Product-of-sums Forms 2016 Simplifying Logic Circuits • A Sum-of-products (SOP) expression will • The circuits below both provide the same output, appear as two or more AND terms ORed but the lower one is clearly less complex. together. ABC ABC AB ABC C D D • A Product-of-sums(POS) expression is sometimes used in logic design. • We will study simplifying logic circuits using Boolean algebra and Karnaugh mapping (A B C)(A B C) 3 4 Digital Systems, Chapter 3 1
2. dce dce 2016 Karnaugh Map Method 2016 Karnaugh Map Method • A graphical method of simplifying logic • The truth table values are placed in the equations or truth tables. Also called a K K map. map. • Adjacent K map square differ in only • Theoretically can be used for any number one variable both horizontally and of input variables, but practically limited to vertically. 5 or 6 variables. • The pattern from top to bottom and left to right must be in the form AB, AB, AB, AB • A SOP expression can be obtained by ORing all squares that contain a 1. 9 10 dce dce 2016 Karnaugh Map Method 2016 Karnaugh Map for 2, 3 variables • Looping adjacent groups of 2, 4, or 8 1s • Looping adjacent groups of 2, 4, or 8 1s will result in will result in further simplification. further simplification. • When the largest possible groups have been looped, only the common terms are placed in the final expression. • Looping may also be wrapped between top, bottom, and sides. 11 12 Digital Systems, Chapter 3 3
3. dce dce 2016 Example of grouping of eight 1s (octals) 2016 Complete Simplification Process • Complete K map simplification process: – Construct the K map, place 1s as indicated in the truth table. – Loop 1s that are not adjacent to any other 1s. – Loop 1s that are in pairs – Loop 1s in octets even if they have already been looped. – Loop quads that have one or more 1s not already looped. – Loop any pairs necessary to include 1st not already looped. – Form the OR sum of terms generated by each loop. 17 18 dce dce 2016 Example 2016 Example 19 20 Digital Systems, Chapter 3 5
4. dce dce 2016 Terminology: Minterms 2016 Terminology: Sum of minterms form • A minterm is a special product of literals, in which each input • Every function can be written as a sum of minterms, which is a variable appears exactly once. special kind of sum of products form n • A function with n variables has 2 minterms (since each variable can • The sum of minterms form for any function is unique appear complemented or not) • If you have a truth table for a function, you can write a sum of • A three-variable function, such as f(x,y,z), has 23 = 8 minterms: minterms expression just by picking out the rows of the table where x’y’z’ x’y’z x’yz’ x’yz the function output is 1. xy’z’ xy’z xyz’ xyz f = x’y’z’ + x’y’z + x’yz’ + x’yz + xyz’ x y z f(x,y,z) f’(x,y,z) • Each minterm is true for exactly one combination of inputs: = m0 + m1 + m2 + m3 + m6 0 0 0 1 0 = m(0,1,2,3,6) Minterm Is true when Shorthand 0 0 1 1 0 x’y’z’ x=0, y=0, z=0 m0 0 1 0 1 0 f’ = xy’z’ + xy’z + xyz x’y’z x=0, y=0, z=1 m 1 0 1 1 1 0 = m + m + m x’yz’ x=0, y=1, z=0 m 4 5 7 2 1 0 0 0 1 = m(4,5,7) x’yz x=0, y=1, z=1 m 3 1 0 1 0 1 xy’z’ x=1, y=0, z=0 m 4 1 1 0 1 0 f’ contains all the minterms not in f xy’z x=1, y=0, z=1 m5 1 1 1 0 1 xyz’ x=1, y=1, z=0 m6 xyz x=1, y=1, z=1 m7 25 26 dce dce 2016 Minterms and Maxterms & Binary representations 2016 SOP-POS Conversion A B C Min- Max- • Minterm values present in SOP expression terms terms not present in corresponding POS 0 0 0 A.B.C A B C expression 0 0 1 A.B.C A B C • Maxterm values present in POS 0 1 0 A.B.C A B C expression not present in corresponding 0 1 1 A.B.C A B C SOP expression 1 0 0 A.B.C A B C 1 0 1 A.B.C A B C 1 1 0 A.B.C A B C 1 1 1 A.B.C A B C 27 28 Digital Systems, Chapter 3 7
5. dce dce 2016 Simplification of POS expressions using K-map 2016 Simplification of POS expressions using K-map • Mapping of expression • Forming of Groups of 0s (A B).(B C) • Each group represents sum term 0 1 AB\C 00 01 11 10 00 0 0 A\BC 0 0 0 1 1 01 1 1 1 1 1 1 0 11 1 1 10 0 1 (A B).(A B C) dce dce 2016 Simplification of POS expressions using K-map 2016 Example 1 • Use a K map to simplify (all possible cases) (A C).(C D).(B C D) 1. F(A,B,C) = (1, 2, 3, 4, 6, 7) 2. F(A,B,C,D) = (1, 3, 4, 5, 6, 7, 12, 13) AB\CD 00 01 11 10 3. F(A,B,C,D) = (2, 5, 7, 8, 10, 12, 13, 15) 00 0 0 1 0 4. F(A,B,C,D) = (0, 6, 8, 9, 10, 11, 13, 14, 15) 5. F(A,B,C,D) = (0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15) 01 0 0 1 1 6. F(D,C,B,A) = (0, 2, 3, 5, 7, 8, 10, 11, 12, 13, 14, 15) 7. F(D,C,B,A) = 0, 1, 4, 5, 7, 8, 10, 13, 14, 15 11 1 0 1 1 8. F(D,C,B,A) = 10 1 0 1 0 1, 2, 5, 10, 12 + (0, 3, 4, 8, 13, 14, 15) Digital Systems, Chapter 3 9
6. dce dce 2016 Assignment 2016 K Map Method Summary • Use a Karnaugh map to reduce each expression to a • Compared to the algebraic method, the K-map process minimum SOP form: is a more orderly process requiring fewer steps and • a) X = A+ B’C + CD always producing a minimum expression. • b) X = A’ B’ C D + A’ B’ C’ D + A B C D + A B C D’ • The minimum expression in generally is NOT unique. • c) X = A’ B(C’ D’ + C’ D) + AB(C’ D’ + C’D) + A B’ C’ D • For the circuits with large numbers of inputs (larger than • d) X = (A’ B’ + A B’)(CD + C D’) four), other more complex techniques are used. • e) X = A’ B’ + A B’ + C’ D’ + C D’ • F) f2(A, B, C, D) = Σm(0, 1, 3, 4, 8, 11) • g) f (w, x, y, z) = Σ m (1,3,4,7,11) + d(5, 12, 13, 14, 15) 41 42 dce dce 2016 Summary 2016 Example • The following function is in minimum sum of products • SOP and POS –useful forms of Boolean equations form. Implement it using only two-input NAND gates. • Design of a comb. Logic circuit No gate may be used as a NOT gate. – (1) construct its truth table, (2) convert it to a SOP, (3) • f = w' y' z + x y' + w y z + x' y z' simplify using Boolean algebra or K mapping, (4) • = y' (w' z + x) + y (w z + x' z') implement • K map: a graphical method for representing a circuit’s truth table and generating a simplified expression • “Don’t cares” entries in K map can take on values of 1 or 0. Therefore can be exploited to help simplification 43 44 Digital Systems, Chapter 3 11
7. dce dce 2016 Enable/Disable Circuits 2016 Enable/Disable Circuits • A circuit is enabled when it allows the • AND gate function act as enable/disable passage of an input signal to the output. circuits • A circuit is disabled when it prevents the passage of an input signal to the output. • Situations requiring enable/disable circuits occur frequently in digital circuit design. 49 50 dce dce 2016 Enable/Disable Circuits 2016 Merging & Inversion Circuits • Design a logic circuit that will allow a signal to pass • OR gate performs signal merging function to the output only when control inputs B and C are both HIGH; otherwise, the output will stay LOW. • Design a logic circuit that will allow a signal to pass • XOR gate performs selectable inversion function to the output only when one, but not both, of the control inputs are HIGH; otherwise, the output will stay HIGH. 51 52 Digital Systems, Chapter 3 13
8. dce dce 2016 Basic Characteristics of Digital ICs 2016 Basic Characteristics of Digital ICs • The CMOS family consists of several series, • Power (referred to as VCC) and ground connections are some of which are shown in the table. required for chip operation. • VCC for TTL devices is normally +5 V. • VDD for CMOS devices can be from +3 to +18 V. 57 58 dce dce 2016 Basic Characteristics of Digital ICs 2016 Troubleshooting Digital Systems • Inputs that are not connected are said to be • 3 basic steps floating. The consequences of floating inputs – Fault detection, determine operation to expected differ for TTL and CMOS. operation. – Floating TTL input acts like a logic 1. The voltage – Fault isolation, test and measure to isolate the fault. measurement may appear in the indeterminate – Fault correction, repair the fault. range, but the device will behave as if there is a 1 on • Good troubleshooting skills come through the floating input. experience in actual hands-on troubleshooting. – Floating CMOS inputs can cause overheating and damage to the device. Some ICs have protection • The basic troubleshooting tools used here will circuits built in, but the best practice is to tie all be: the logic probe, oscilloscope, and logic unused inputs either high or low. pulser. • The most important tool is the technician’s brain. 59 60 Digital Systems, Chapter 3 15
9. dce dce 2016 External Faults 2016 External Faults • Shorted signal lines – the same signal will • Faulty power supply – ICs will not operate or appear on two or more pins. VCC or ground will operate erratically. may also be shorted. Some causes: – May lose regulation due to an internal fault or – Sloppy wiring because circuits are drawing too much current. – Solder bridges – Always verify that power supplies are providing the – Incomplete etching specified range of voltages and are properly • Detect visually and verify with an ohmmeter. grounded. – Use an oscilloscope to verify that AC signals are not present. 65 66 dce dce 2016 External Faults 2016 Programmable Logic Devices • PLDs allow the design process to be automated. • Output loading – caused by connecting too • Designers identify inputs, outputs, and logical relationships. many inputs to the output of an IC. • PLDs are electronically configured to form the defined logic – Causes output voltage to fall into the indeterminate circuits. range. – This is called loading the output. – Usually a result of poor design or bad connection. 67 68 Digital Systems, Chapter 3 17