Bài giảng Digital Systems - Chapter 4: Objectives - Nguyễn Trần Hữu Nguyên

Nội dung text: Bài giảng Digital Systems - Chapter 4: Objectives - Nguyễn Trần Hữu Nguyên

1. dce dce 2017 2017 Chapter 4 Objectives • Selected areas covered in this chapter: – Converting logic expressions to sum-of-products expressions. – Boolean algebra and the Karnaugh map as tools to simplify and design logic circuits. Digital Systems – Operation of exclusive-OR & exclusive-NOR circuits. – Designing simple logic circuits without a truth table. – Basic characteristics of TTL and CMOS digital ICs. Nguyễn Trần Hữu Nguyên – Basic troubleshooting rules of digital systems. BK TP.HCM D: Computer Engineering – Programmable logic device (PLD) fundamentals. – Hierarchical design methods. E: nthnguyen@hcmut.edu.vn – Logic circuits using HDL control structures IF/ELSE, IF/ELSIF, and CASE. 2 1 2 dce dce 2017 4-1 Sum-of-Products Form 2017 4-1 Sum-of-Products Form • A Sum-of-products (SOP) expression will appear • The product-of-sums (POS) form consists of as two or more AND terms ORed together. two or more OR terms (sums) ANDed together. 3 4 3 4 Digital Logic Design 1 1
2. dce dce 2017 4-3 Algebraic Simplification 2017 4-4 Designing Combinational Logic Circuits Simplifed logic circuit. • To solve any logic design problem: – Interpret the problem and set up its truth table. – Write the AND (product) term for each case where output = 1. – Combine the terms in SOP form. – Simplify the output expression if possible. – Implement the circuit for the final, simplified expression. z = A(C + B) Circuit that produces a 1 output only for the A = 0, B = 1 condition. 9 10 9 10 dce dce 2017 4-4 Designing Combinational Logic Circuits 2017 4-4 Designing Combinational Logic Circuits An AND gate with appropriate inputs can be used to Each set of input conditions that is to produce a produce a HIGH output for a specific set of input levels. 1 output is implemented by a separate AND gate. The AND outputs are ORed to produce the final output. 11 12 11 12 Digital Logic Design 1 3
3. dce dce 2017 4-5 Karnaugh Map Method 2017 4-5 Karnaugh Map Method Four-variable K-Map. Looping 1s in adjacent groups of 2, 4, or 8 will result in further simplification. Looping groups of 2 (Pairs) Adjacent K map square differ in only one variable both horizontally and vertically. Groups of 4 Groups of 8 (Quads) (Octets) A SOP expression can be obtained by ORing all squares that contain a 1. 17 18 17 18 dce dce 2017 4-5 Karnaugh Map Method 2017 4-5 Karnaugh Map Method • When the largest possible groups have been • Complete K map simplification process: looped, only the common terms are placed – Construct the K map, place 1s as indicated in the truth table. – Loop 1s that are not adjacent to any other 1s. in the final expression. – Loop 1s that are in pairs. – Looping may also be wrapped between top, bottom, – Loop 1s in octets even if they have already been looped. and sides. – Loop quads that have one or more 1s not already looped. – Loop any pairs necessary to include 1st not already looped. – Form the OR sum of terms generated by each loop. When a variable appears in both complemented and uncomplemented form within a loop, that variable is eliminated from the expression. Variables that are the same for all squares of the loop must appear in the final expression. 19 20 19 20 Digital Logic Design 1 5
4. dce dce 2017 4-6 Exclusive OR and Exclusive NOR Circuits 2017 4-6 Exclusive OR and Exclusive NOR Circuits Exclusive NOR circuit and truth table. Traditional XNOR gate symbol. An XNOR gate has only two inputs, combined so that x = AB + AB. A shorthand way indicate the XOR output expression is: x = A B. XNOR represents inverse of the XOR operation. Output is HIGH only when the two inputs are at the same level. Output expression: x = AB + AB Quad XNOR chips with four XNOR gates. 74LS266 Quad XNOR (TTL family) XNOR produces a HIGH output whenever 74C266 Quad XOR (CMOS) the two inputs are at the same levels. 74HC266 Quad XOR (high-speed CMOS) 25 26 25 26 dce dce 2017 4-6 Exclusive OR and Exclusive NOR Circuits 2017 4-6 Exclusive OR and Exclusive NOR Circuits Truth table and circuit for detecting equality of How an XNOR gate may two-bit binary numbers. be used to simplify circuit implementation. 27 28 27 28 Digital Logic Design 1 7
5. dce dce 2017 4-8 Enable/Disable Circuits 2017 4-8 Enable/Disable Circuits A logic circuit that will allow a signal to pass to output A logic circuit with input signal A, control only when one, but not both control inputs are HIGH. input B, and outputs X and Y, which operates as: Otherwise, output will stay HIGH. When B = 1, output X will follow input A, and output Y will be 0. When B = 0, output X will be 0, and output Y will follow input A. 33 34 33 34 dce dce 2017 4-9 Basic Characteristics of Digital ICs 2017 4-9 Basic Characteristics of Digital ICs • IC “chips” consist of resistors, diodes & transistors • The dual-in-line package (DIP) contains two fabricated on a piece of semiconductor material parallel rows of pins. called a substrate. Digital ICs are often categorized by complexity, according to the number of logic gates on the substrate. The DIP is probably the most common digital IC package found in older digital equipment. 35 36 35 36 Digital Logic Design 1 9
6. dce dce 2017 4-9 Basic Characteristics of Digital ICs 2017 4-9 Basic Characteristics of Digital ICs VCC for TTL devices is normally +5 V. The transistor-transistor logic (TTL) family consists of subfamilies shown here: Power (VCC) and ground connections are required for chip operation. Differences between the TTL devices is limited to electrical characteristics such as power dissipation & switching speed. TTL Pin layout and logic operations are the same. INVERTER 41 42 41 42 dce dce 2017 4-9 Basic Characteristics of Digital ICs 2017 4-9 Basic Characteristics of Digital ICs V for CMOS The Complimentary Metal-Oxide Semiconductor DD devices can be Power (VDD) and (CMOS) family consists of several series from +3 to +18 V. ground connections are required for chip operation. CMOS INVERTER CMOS devices perform the same function as, but are not necessarily pin for pin compatible with TTL devices. 43 44 43 44 Digital Logic Design 1 11
7. dce dce 2017 4-10 Troubleshooting Digital Systems 2017 4-10 Troubleshooting Digital Systems • Three basic steps in fixing a digital circuit or system that has a fault (failure): The logic probe will indicate the presence or absence – Fault detection—determine operation to expected of a signal when touched to a pin as indicated below. operation. – Fault isolation—test & measure to isolate the fault. – Fault correction—repair the fault. • The basic troubleshooting tools are the logic probe, oscilloscope, and logic pulser. 49 50 49 50 dce dce 2017 4-11 Internal Digital IC Faults 2017 4-11 Internal Digital IC Faults • Most common internal failures: These two types of failures force the input signal – Malfunction in the internal circuitry. at the shorted pin to stay in the same state. • Outputs do not respond properly to inputs. Left—IC input internally shorted to ground. • Outputs are unpredictable. Right—IC input internally shorted to supply voltage. – Inputs or outputs shorted to ground or VCC . • The input will be stuck in LOW or HIGH state. – Inputs or outputs open-circuited . • An open output will result in a floating indication. • Floating input in a TTL will result in a HIGH output. • Floating input in a CMOS device will result in erratic or possibly destructive output. – Short between two pins (other than ground or VCC). • The signal at those pins will always be identical. 51 52 51 52 Digital Logic Design 1 13
8. dce dce 2017 4-12 External Faults 2017 4-12 External Faults What is the most probable fault in the circuit shown? • Shorted signal lines—the same signal appears on two or more pins—and VCC or ground may also be shorted, caused by: – Sloppy wiring. – Solder bridges. – Incomplete etching. • This type of fault can be detected visually and verified with an ohmmeter between the points The indeterminate level at the NOR gate output is in question. probably due to the indeterminate input at pin 2. Because there is a LOW at Z1-6, this LOW should also be at Z2-2. 57 58 57 58 dce dce 2017 4-12 External Faults 2017 4-12 External Faults • Faulty power supply—ICs will not operate or • Output loading—caused by connecting too many will operate erratically. inputs to the output of an IC, exceeding output – May lose regulation due to an internal fault or current rating. because circuits are drawing too much current. – Output voltage falls into the indeterminate range. • Verify that power supplies provide the specified • Called loading the output signal. range of voltages and are properly grounded. – Usually a result of poor design or bad connection. – Use an oscilloscope to verify that AC ripple is not present and verify that DC voltages stay regulated. • Some ICs are more tolerant of power variations and may operate properly—others do not. – Check power and ground levels at each IC that appears to be operating incorrectly. 59 60 59 60 Digital Logic Design 1 15
9. dce dce 2017 The IF-ELSE Statement - MUX 4 TO 1 2017 MUX 16 to 1 with MUX 4 TO 1 module mux4to1 (W, S, z); module mux16to1 (W, S, OUT); input [3:0] W; input [15:0] W; input [1:0] S; input [3:0] S; output reg z; wire [3:0] M; always @(*) output OUT; if (S == 0) z = W[0]; mux4to1 MUX1 (W[3:0], S[1:0], M[0]); else if (S = 1) mux4to1 MUX2 (W[7:4], S[1:0], M[1]); z = W[1]; mux4to1 MUX3 (W[11:8], S[1:0], M[2]); else if (S == 2) mux4to1 MUX4 (W[15:12], S[1:0], M[3]); z = W[2]; else mux4to1 MUX5 (M[3:0], S[3:2], OUT); z = W[3]; endmodule endmodule 65 66 65 66 dce 2017 The CASE Statement module mux4to1 (W, S, f); case (expression) input [0:3]W; alternative1: statement; input [1:0] S; alternative2: statement; output reg f; · always @(W, S) · case (S) · 0: f = W[0]; alternativej: statement; 1: f = W[1]; [default: statement;] 2: f = W[2]; endcase 3: f = W[3]; endcase endmodule 67 67 Digital Logic Design 1 17