Bài giảng Digital Systems - Chapter 5: Arithmetic

Nội dung text: Bài giảng Digital Systems - Chapter 5: Arithmetic

1. dce dce 2018 2018 Introduction • Digital circuits are frequently used for arithmetic operations • Fundamental arithmetic operations on binary Digital Systems numbers and digital circuits which perform arithmetic operations will be examined. Arithmetic BK TP.HCM 2 dce dce 2018 Binary Addition 2018 Binary Addition • Binary numbers are added like decimal • 0 + 0 = 0 numbers. • 1 + 0 = 1 • In decimal, when numbers sum more than 9 a • 1 + 1 = 0 + carry 1 carry results. • 1 + 1 + 1 = 1 + carry 1 • In binary when numbers sum more than 1 a • E.g.: carry takes place. 1010 (10) 001 (1) • Addition is the basic arithmetic operation used by digital devices to perform subtraction, +1100 (12) +101 (5) multiplication, and division. 10110 (22) +111 (7) 1101 (13) 3 4 1
2. dce dce 2018 Why 2’s complement representation? 2018 Comparison Table • If we represent signed numbers in 2’s complement form, subtraction is the same as addition to negative (2’s • Note the "wrap- complemented) number. around" effect 27 0001 1011 b of the binary - 17 0001 0001 b representation + 10 0000 1010 b – i.e. The top of the table wraps + 27 0001 1011 b + - 17 1110 1111 b around to the + 10 0000 1010 b bottom of the table • Note that the range for 8-bit unsigned and signed numbers are different. • 8-bit unsigned: 0 +255 • 8-bit 2’s complement signed number: -128 +127 9 10 dce dce 2018 Sign Extension 2018 Sign Extension • How to translate an 8-bit 2’s complement • Sometimes we need to extend a number into more bits number to a 16-bit 2’s complement • Decimal number? – converting 12 into a 4 digit number gives 0012 – we add 0's to the left-hand side • Unsigned binary – converting 0011 into an 8 bit number gives 00000011 – we add 0's to the left-hand side • For signed numbers we duplicate the sign bit (MSB) • Signed binary – converting 0011 into 8 bits gives 00000011 (duplicate the 0 MSB) – converting 1011 into 8 bits gives 11111011 (duplicate the 1 MSB) • This operation is known as sign extension. – Called "Sign Extension" 11 12 3
3. dce dce 2018 2018 Subtraction in the 2’s Complement System Multiplication and Division by 2N • The number subtracted (subtrahend) is negated. • In decimal, multiplying by 10 can be achieved • The result is added to the minuend. by • The answer represents the difference. – shifting the number left by one digit adding a zero at the LS digit • If the answer exceeds the number of magnitude • In binary, this operation multiplies by 2 bits an overflow results. • In general, left shifting by N bits multiplies by 2N – zeros are always brought in from the right-hand end – E.g. 17 18 dce dce 2018 Multiplication of Binary Numbers 2018 Binary Division • This is similar to multiplication of decimal • This is similar to decimal long division. numbers. • It is simpler because only 1 or 0 are possible. • Each bit in the multiplier is multiplied by the multiplicand. • The subtraction part of the operation is done using 2’s complement subtraction. • The results are shifted as we move from LSB to MSB in the multiplier. • If the signs of the dividend and divisor are the • All of the results are added to obtain the final same the answer will be positive. product. • If the signs of the dividend and divisor are different the answer will be negative. 19 20 5
4. dce dce 2018 Arithmetic Circuits 2018 Binary Addition • Typical sequence of operations: • Recall the binary addition process A 1 0 0 1 – Control unit is instructed to add a specific number from a memory location to a number stored in the + B 0 0 1 1 accumulator register. S 1 1 0 0 – The number is transferred from memory to the B • LS Column has 2 inputs 2 outputs register. – Inputs: A0 B0 – Number in B register and accumulator register are – Outputs: S0 C1 added in the logic circuit, with sum sent to • Other Columns have 3 inputs, 2 outputs accumulator for storage. – Inputs: An Bn Cn – The new number remains in the accumulator for – Outputs: Sn Cn+1 further operations or can be transferred to memory – We use a "half adder" to implement the LS column for storage. – We use a "full adder" to implement the other columns – Each column feeds the next-most-significant column. 25 26 dce dce 2018 Parallel Binary Adder 2018 Half Adder • The A and B variables represent 2 binary numbers to • Truth Table be added. The C variables are the carries. The S variables are the sum bits. • Boolean Equations • Implementation 27 28 7
5. dce dce 2018 Adder Example 2018 Hierarchy • Any Verilog design you do will be a module • This includes testbenches! • Interface (“black box” representation) – Module name, ports • Definition – Describe functionality of the block – Includes interface • Instantiation – Use the module inside another module 33 34 dce dce 2018 Hierarchy 2018 Add_half Module • Build up a module from smaller pieces – Primitives Add_half – Other modules (which may contain other modules) xor and • Design: typically top-down module Add_half(c_out, sum, a, b); • Verification: typically bottom-up output sum, c_out; Full Adder Hierarchy Add_full input a, b; xor sum_bit(sum, a, b); Add_half Add_half or and carry_bit(c_out, a, b); endmodule xor and xor and 35 36 9
6. dce dce 2018 2018 Parallel Adder Complete Parallel Adder With Registers • Uses 1 full adder per bit of the numbers • Register notation – to indicate the contents of a register • The carry is propagated from one stage to the next we use brackets: most significant stage [A]=1011 is the same as A3=1, A2=0, A1=1, A0=1 – takes some time to work because of the carry propagation delay • A transfer of data to or from a register is indicated with which is n times the propagation delay of one stage. an arrow – [B] [A] means the contents of register B have been transferred to register A. • Eg.: 1001 + 0101 using the parallel adder: – t1 : A CLR pulse is applied – t2 : 1001 from mem-> B – t3 : 1001 + 0000 -> A – t4 : 0101 from mem-> B – t5 : The sum outputs -> A – The sum of the two numbers is now present in the accumulator. 41 42 dce dce 2018 Complete Parallel Adder With Registers 2018 Carry Propagation • Parallel adder speed is limited by carry propagation (also called carry ripple). • Carry propagation results from having to wait for the carry bits to “ripple” through the device. • Additional bits will introduce more delay. • Various techniques have been developed to reduce the delay. The look-ahead carry scheme is commonly used in high speed devices. 43 44 11
7. dce dce 2018 Parallel adder/subtractor using the 2’s- 2018 ALU Integrated Circuits complement system ADD = 1, SUB = 0: B register passes to adder and Carry in = 0 ADD = 0, SUB = 1: • ALUs can perform Complement of B register different arithmetic and passes to adder and Carry logic functions as in = 1 determined by a binary code on the function select inputs. 49 50 dce 2018 Two 74HC382 ALU chips connected as an eight-bit adder 51 13